The present invention relates generally to an image decoding system. More specifically, the invention relates to an image decoding system for decoding packed data while depacking the data.
In image coding and decoding techniques, a packing/depacking processing means a processing for cutting a long variable-length code, which has a length exceeding the upper limit to length, in the middle thereof to store the cut code in a block having left capacity, in order to store variable-length codes, which have different lengths every block, in an area having a predetermined capacity, and means a so-called “processing for accommodating a data storing capacity of one block to that of the other block”.
It is supposed that the packing/depacking processing according to the present invention uses, e.g., a “DV format”, i.e., a format of a system called DVC (Digital VCR for Consumer use) standardized by “HD digital VCR Conference”. However, the format used for the packing/depacking processing according to the present invention should not always be limited to the above described format, but the invention may be widely applied to a processing for depacking a variable-length coded image data packed by another predetermined format.
Since the details of the packing/depacking processing is described in required documents (e.g., “Illustrated Digital Video Reader” written and edited by Kubota, etc.), see these documents.
The depacking processing is a processing for cutting/concatenating data, which are divided to be stored in a plurality of blocks, to reproduce the original variable-length code string. However, if an inverse processing to packing is simply carried out, it is required to provide a memory (about 4400 bits) for temporarily storing concatenated data. Therefore, a system for realizing memory saving by avoiding insuring a memory to the utmost and by using many pointer operations has been proposed in, e.g., Japanese Patent Laid-Open No. 8-275162.
This conventional decoding circuit is shown in FIG. 1. In FIG. 1, code data inputted to a buffer memory 2 from a main memory 1 are supplied to a barrel shifter 3 every byte by byte information from a code address storing circuit (not shown). A decoding circuit 4 comprises the barrel shifter 3 and a variable-length code table 5. The barrel shifter 3 is designed to shift code data, which have not been decoded, by a code length, which is returned from the variable-length code table 5 of the decoding circuit 4, and by bit information, which is fed from the code address storing circuit (not shown), to connect code data which are supplied from the buffer memory 2.
Furthermore, since FIG. 1 shows only a principal part of FIG. 1 of the above described prior document (Japanese Patent Application No. 8-275162), the code address storing circuit, a block counting circuit and so forth are not shown.
According to this conventional image decoding system, it is possible to omit the memory for temporarily storing concatenated data. However, there is a disadvantage in that accesses to the buffer memory 2 for holding data (3040 bits) for one video segment frequently and irregularly occur to occupy a bus.
Because a system for sequentially supplying data to the barrel shifter “by a space” which is formed by decoding a variable-length code (the supply of data from the buffer memory is carried out every 8 bits) is adopted. For that reason, from the standpoint of the fact that a memory band width is insured, the buffer memory must be substantially separated from the main memory to be insured, so that the memory saving effect is reduced.
Particularly in recent years, in order to further save memories, it is strongly required to intend to arrange data, which are to be decoded, on a main memory to reduce a buffer memory. However, the number of accesses to the main memory increases, so that the determination of the buffer size is an important matter which has a great influence on performance.
After the coding scheme of the DV format was analyzed in detail, the inventors founded that, even if the contents of a processing appear a variable-length code data processing at first sight, a processing for dividing data into formats similar to a 112-bit fixed length processing can be actually carried out. If the size of the buffer memory is fixed to this length and if a memory access is carried out every this length, the degree of occupancy of the memory bus can be greatly reduced.